1. Field of the Invention
The present invention relates to a lead frame for use in a semiconductor device, and more particularly to a lead frame for a semiconductor device capable of enhancing reliability of the semiconductor device, wherein dummy leads attached to a semiconductor chip are provided on one side of a vertically surface-mounted package lead frame opposite from operative inner leads, which is mainly utilized in a mounting method of a semiconductor chip such as a lead-on-chip (hereinafter referred to as LOC) and a chip-on-lead (hereinafter referred to as COL).
2. Background Information
Recent developments in the semiconductor technology have yielded increased semiconductor chip memory capacity, which involves increased numbers of I/O pins, fast signal processing speed, and high power consumption. This increases the need for a dense-packing mounting method. Depending on the trend toward achieving high packing density of the semiconductor chips, the number of leads on the lead frame is increased to shorten the lead spacing and reduce the size of the leads. Therefore, it is difficult to design and manufacture a lead frame with the consequence of requiring continuous changes in the type of semiconductor packages and its manufacturing process and method.
Moreover, because of the high-speed signal processing and increased power dissipation, a large amount of heat is generated from the semiconductor chip. In order to eliminate this heat, a heat sink composed of a material having an excellent thermal diffusion property is usually separately installed in the semiconductor package. In the alternative, the envelope of the semiconductor package is formed of a material having an excellent thermal conductivity.
Additionally, in order to increase the mounting density of the semiconductor chip within an individual unit area, a chip-on-board (COB) method for directly mounting the semiconductor chip on a printed circuit board or stacked package method is currently available. Methods for mounting semiconductor packages have also become increasingly important.
A widely used semiconductor package type is a molding package which is obtained by mounting a semiconductor chip on a die pad of a general lead frame and then forming the envelope of the package using a molding material. This molding package may be classified into a horizontal-type and a vertical-type.
The horizontal-type package which is employed in memory cards and small or thin film-type devices in a personal computer, etc., includes, according to the shape of the packages, a single-in-line package (SIP) having leads projecting on only one side of the package envelope, a dual-in-line package (DIP) having leads projecting on both sides of the envelope, or a quad-flat package (QFP) having leads projecting on all four sides of the envelope.
Meanwhile, the vertical-type package is becoming more common in view of its light weight, large capacity and high speed of the semiconductor device when miniaturization of a substrate is contrived by utilizing an empty space of the substrate having components of different heights, or large amounts of general-purpose memory packages are installed in the major part of a main storage.
In such a vertical-type package, a zigzag-in-line in-line package (ZIP), having leads projecting on one side of the envelope of the package and then inserted into the substrate by being bent in both directions, creates difficulties in multilayer interconnection and an overall reflow on the substrate during a mounting process on both sides of the substrate.
A vertical surface-mount package (hereinafter referred to as a VSMP) 10 shown in FIG. 1 is devised to solve the above-described problem. Here, external leads 11 are bent while projecting on only one side of an envelope 13 of the semiconductor package, and the VSMP 10 is vertically mounted by means of support leads 12 bent in right angled shape in both direction and provided outside of the external leads 11.
As shown in FIG. 2, a plurality of VSMPs can be mounted on a printed circuit board 14, and the multilayer interconnection of the printed circuit board 14 can be attained because the packages are surface-mounted. Furthermore, it is possible to mount the packages on both sides of the printed circuit board 14 and perform an overall reflow of the external leads 11 together with other components.
Since the size of the mounted semiconductor chip is generally small in the above-described VSMPs, a semiconductor chip having a bonding pad around the chip periphery is mounted on a die pad, and a semiconductor chip having a bonding pad concentrated on the center thereof is mounted by means of the COL or LOC method.
One example of the conventional vertically surface-mounted package 15 having such a semiconductor chip is shown in FIG. 3. Here, a semiconductor chip 16 has a plurality of bonding pads on its center, and a plurality of internal leads 17 are regularly spaced on the upper portion of the semiconductor chip 16 while being arranged toward the upper and lower directions of the semiconductor chip 16. A plurality of wires 18 respectively connect the bonding pads formed on the semiconductor chip 16 to the internal leads 17. A reference numeral 19 designates a protective envelope of the semiconductor package for encapsulating the internal leads 17 and the semiconductor chip 16. A plurality of external leads 20 project outwardly on one side of the envelope 19 of the package. Support leads 21 of an open square shape bent in opposite directions are installed for supporting the vertically surface-mounted package 15 outside of the external leads 20. This vertically surface-mounted package 15 has a relatively small semiconductor chip 16, but the internal leads are difficult to form on the upper portion of the semiconductor chip to increase the memory capacity of the semiconductor chip.
FIG. 4 shows another example of the conventional vertically surface-mounted package, wherein semiconductor chip 23 is larger than that shown in FIG. 3. Because the cavity within the semiconductor package 22 is narrow, internal leads 24 attached on the semiconductor chip 23 are arranged generally in the direction of the projecting external leads 25. This type of the vertically surface-mounted package is illustrated in U.S. Pat. No. 4,951,122.
In the lead frame of the above-described vertically surface-mounted package, the semiconductor chip having bonding pads on its center is attached and then molded to the internal leads by means of the COL or LOC method.
At this time, since the internal leads are arranged in the direction of the external leads, all leads are gathered in only one side. Therefore, during a molding process, inflow pressure of a molding resin into the cavity is inconsistent between the side with the leads and the side without, and can cause deformation of the internal leads and wires. This results in short circuits or line disconnection, thereby degrading reliability of the semiconductor package.